Scientists develop new test method for chip aging

Chinese researchers claim to have developed a new faster and more efficient methodology for testing the longevity of semiconductors.

The new methodology, published in the journal, Microelectronics Reliability, uses a high-efficiency aging test technique that its developers say can reduce the test time while increasing its accuracy.

Semiconductors deteriorate in quality over time due to factors including weathering and continuous use. A number of testing methodologies already exist to measure the effects of this aging, including time-dependent dielectric breakdown (TDDB) and bias temperature instability (BTI).

The research team from China’s Hangzhou Dianzi University’s School of Electronic Information said the new method as “an intuitive and efficient test approach is introduced, which determines the voltage stress and the corresponding test time according to the degradation of the median value of device electrical indicators.”

“It is demonstrated to be a fast, accurate, and low-cost test method for device degradation,” the researchers said. “Additionally, based on multi-group tests data, a weighted average method is presented to improve the accuracy of data fitting.”

The team said the new method is five time faster than conventional testing methods, and can be applied to existing methods like BTI and TDDB.